The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of, and attention to, semiconductor material properties and behaviors.
The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Every device must be smaller without damaging the operating characteristics of the integrated circuit devices. High packing density, low heat generation, and low power consumption, with good reliability and long operation life must be maintained without any functional device degradation. Increased packing density of integrated circuits is usually accompanied by smaller feature size.
As integrated circuits become denser, the widths of interconnect layers that connect transistors and other semiconductor devices of the integrated circuit are reduced. As the widths of interconnect layers and semiconductor devices decrease, their resistance increases. As a result, semiconductor manufacturers seek to create smaller and faster devices by using, for example, a copper interconnect instead of a traditional aluminum interconnect. Unfortunately, copper is very difficult to etch in most semiconductor process flows. Therefore, damascene processes have been proposed and implemented to form copper interconnects.
Damascene methods usually involve forming a trench and/or an opening in a dielectric layer that lies beneath and on either side of the copper-containing structures. Once the trenches or openings are formed, a blanket layer of the copper-containing material is formed over the entire device. Electrochemical deposition (ECD) is typically the only practical method to form a blanket layer of copper. The thickness of such a layer must be at least as thick as the deepest trench or opening. After the trenches or openings are filled with the copper-containing material, the copper-containing material over them is removed, e.g., by chemical-mechanical polishing (CMP), so as to leave the copper-containing material in the trenches and openings but not over the dielectric or over the uppermost portion of the trench or opening.
Unfortunately, however, copper tends to be rather difficult to deposit directly on dielectric via ECD, due largely to the material properties of copper and most common dielectric materials. Often, a relatively thick layer of copper will not adhere to a dielectric in a uniform and stable manner. Obviously, this can cause a number of semiconductor yield and reliability problems. Therefore, a thin starter layer of copper—a seed layer—is usually deposited on the dielectric first. The deposition of this relatively thin layer—on the order of 100 Å–1000 Å, depending on contour of the surface—provides for more stable and uniform initial application of copper to the dielectric. Once this seed layer is in place, thicker layers of copper may be plated directly on the copper “seed”. The thicker copper adheres well to the copper “seed”, resulting—in theory—in a more uniform and stable copper plating.
Even though the seed layer approach eliminates some of the copper/dielectric interface problems, other complications arise from contamination of the seed layer. In many conventional fabrication processes, seed layer deposition and the final copper ECD are performed in different apparatus. The handling, transfer, and queuing of a substrate that has just completed seed layer deposition provides a number of potential contamination sources—airborne gases or molecular particles, for example—that can cause pits and other anomalies in the seed layer surface. Typically, seed layers have a very high affinity for even minute amounts of contaminants. Even if only exposed for a minimal time, the relative concentration of such contaminants on the seed layer surface can increase dramatically—causing any number of structural anomalies. These anomalies in the seed layer surface can disrupt or inhibit the copper ECD process. For example, certain anomalies can render the seed layer surface hydrophobic, causing voids and other unstable or incomplete copper device structures to form during a plating process. Increased yield losses, device failures, and reliability problems result.
Certain difficulties of conventional processes are illustrated now in reference to prior art FIG. 1, which depicts a conventional fabrication process 100 involving seed layer handling. A substrate 102 is removed, directly or indirectly, by an operator 104 from a first processing apparatus 106 (e.g., a sputtering system), in which a seed layer is applied to substrate 102. Operator 104 then queues substrate 102 for processing by a second processing apparatus 108 (e.g., an ECD system). During its transition from apparatus 102 to apparatus 108, substrate 102 may be exposed to a number of contaminants 110 (e.g., airborne gases or particles).
The length of time that substrate 102 is exposed to contaminants 110 can vary widely, depending upon, for example, the amount of handling involved, the queue times at each apparatus, and the physical proximity of the apparatus. At worst, substrate 102 may be exposed to contaminants 110 for extended periods of time after extensive handling. Even in a best-case scenario—where apparatus 102 and 108 are proximal to one another, and handling by operator 104 and queue times are minimized—substrate 102 is still exposed to contaminants 110 long enough to incur some anomalies.
Some attempts have been made to address the problems arising from seed layer contamination. One such attempt involves storing substrates, after seed layer deposition and prior to ECD, in an inert environment (e.g., storage in nitrogen gas). Other attempts involve cleaning or repair of the seed layer prior in a separate apparatus prior to loading the substrate into ECD apparatus. Isolation methods are effective for the period of time that a substrate is stored in isolation, but fail to address exposure and handling involved in transferring substrates into and out of storage. Often, certain cleaning approaches are ineffective for particular contaminant chemistries. Cleaning approaches can also further damage, or even remove, significant portions of the seed layer—rendering the seed layer unusable. Seed repair methods often involve some measure of re-deposition of the seed layer—adding potentially numerous and costly extra processing steps. Importantly, most all such approaches fail to eliminate the exposure of the seed layer surface to some contamination during transfer between the distinct processing apparatus involved.
As a result, there is a need for a seed layer remediation system that effectively neutralizes seed layer contamination, providing non-destructive seed layer remediation in an easy, efficient and cost-effective manner.